Stanford Root

Schedule

Stanford Root

Schedule

EE 316

Advanced VLSI Devices

UNITS:3
GRADING:Letter (ABCD/NP)
LEVEL:Graduate
GER:—

In modern VLSI technologies, device electrical characteristics are sensitive to structural details and therefore to fabrication techniques. How are advanced VLSI devices designed and what future changes are likely? What are the implications for device electrical performance caused by fabrication techniques? Physical models for nanometer scale structures, control of electrical characteristics (threshold voltage, short channel effects, ballistic transport) in small structures, and alternative device structures for VLSI.

Syllabus for selected term:
View Winter 2027 Syllabus

Sections

1 Term
Lecture 1Open
ID: 25105
0 / 50 enrolled
DAYS:Tuesday, Thursday
TIME:1:30 PM – 2:50 PM
LOCATION:TBD
INSTRUCTOR:
Wong, H.S.Philip
3units

EE 316: Advanced VLSI Devices

3 units · Letter (ABCD/NP)

In modern VLSI technologies, device electrical characteristics are sensitive to structural details and therefore to fabrication techniques. How are advanced VLSI devices designed and what future changes are likely? What are the implications for device electrical performance caused by fabrication techniques? Physical models for nanometer scale structures, control of electrical characteristics (threshold voltage, short channel effects, ballistic transport) in small structures, and alternative device structures for VLSI.

Offered in Winter 2027 at Stanford University.

Winter 2027 sections

  • Lecture — Tuesday Thursday 1:30 PM – 2:50 PM — Wong, H.S.Philip (Graduate)

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