Stanford Root

Schedule

Stanford Root

Schedule

EE 372B

Silicon Bring-Up: Post-Silicon Validation and Characterization

UNITS:3
GRADING:Letter or Credit/No Credit
LEVEL:Graduate
GER:—

This hands-on course guides students through the complete workflow of bringing up and validating a fabricated integrated circuit in a modern CMOS process. The course uses chips designed and fabricated in a preceding tapeout course, in which students design and fabricate analog low-dropout (LDO) regulators; however, prior participation in the design course is not required. Students will learn to interface with packaged devices, develop measurement setups, and use industry-standard lab equipment to characterize performance. Topics include PCB and test fixture design, automated data collection, post-silicon characterization across process, voltage, and temperature, and systemic debug of discrepancies between simulation and measurement. Working in small teams, students will bring up fabricated designs, diagnose silicon-level issues, and complete a full validation and debug cycle, culminating in a final report and demonstration.

Syllabus for selected term:
View Autumn 2026 Syllabus

Sections

1 Term
Laboratory 1Open
ID: 28440
0 / 30 enrolled
DAYS:Tuesday, Thursday
TIME:1:30 PM – 2:50 PM
LOCATION:Gates B12
INSTRUCTOR:
Sideris, Constantine
3units

EE 372B: Silicon Bring-Up: Post-Silicon Validation and Characterization

3 units · Letter or Credit/No Credit

This hands-on course guides students through the complete workflow of bringing up and validating a fabricated integrated circuit in a modern CMOS process. The course uses chips designed and fabricated in a preceding tapeout course, in which students design and fabricate analog low-dropout (LDO) regulators; however, prior participation in the design course is not required. Students will learn to interface with packaged devices, develop measurement setups, and use industry-standard lab equipment to characterize performance. Topics include PCB and test fixture design, automated data collection, post-silicon characterization across process, voltage, and temperature, and systemic debug of discrepancies between simulation and measurement. Working in small teams, students will bring up fabricated designs, diagnose silicon-level issues, and complete a full validation and debug cycle, culminating in a final report and demonstration.

Offered in Autumn 2026 at Stanford University.

Autumn 2026 sections

  • Laboratory — Tuesday Thursday 1:30 PM – 2:50 PM — Gates B12 — Sideris, Constantine (Graduate)

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